Research on bus arbitration in the hottest multi D

2022-07-25
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Research and implementation of bus arbitration in multi DSP parallel real-time processing system

1. Introduction

at present, DSP (digital signal processor) is widely used in the field of signal processing, especially in radar signal and image signal processing. Many signal processing boards use DSP as the core processing chip. However, with the increasing demand for the processing capacity of signal processing boards, for example, for high frame number The real-time processing of large-scale image sequences often requires the computing power of billions of times per second. At present, the computing power of a single DSP can not meet its requirements. Usually, the signal processing board needs to adopt the multi DSP parallel processing structure in the design to meet the requirements of the system for the amount of computing. Under this multi DSP parallel processing structure, multiple DSPs usually share the bus to realize the gradual expansion of market share and the transfer of data and control status words between each other or with external devices. At this time, the system needs to establish a bus arbitration mechanism to ensure that multiple DSPs will not conflict and compete when using the bus. Especially in the real-time processing environment, it is more necessary to ensure the reliable transfer of bus control between each DSP, Provide guarantee for real-time data exchange between processors. Once the data transmission fails, the system will be delayed or paralyzed. Therefore, whether the design of bus arbitration mechanism is reasonable or not will directly affect the operating efficiency and reliability of the system. Therefore, the bus operation should be fully considered in the system design, which is a very important link in the comprehensive utilization of waste resources

2. Introduction to multi DSP parallel processing system structure

the system structure is shown in Figure 1:

the system is a distributed multi instruction, multi data (MIMD) processing system. The functional modules include: processor module composed of multiple DSPs, shared memory module, input/output device and host. These modules are connected through a shared bus. Each DSP includes arithmetic unit, on-chip memory, on-chip I/O unit, arbitration logic unit and bus interface. Since each DSP has a large capacity of local memory, the instructions and data of each DSP are basically accessed from their own local memory, which will greatly reduce the load of the shared bus

the system works in the mode of master-slave cooperation, that is, after the system is started, the main processor has the highest priority. It controls the bus, is responsible for the initialization of the whole system, data program configuration, communication with the host, etc., and participates in the calculation work. The priority of each slave chip is smaller than that of the master chip, and usually only participates in the operation. If the DSPs are linked with each other through other external ports such as chain junctions, the whole system will reflect a flexible structure, that is, the processing system structure and working mode can be changed through software settings without changing the hardware design

for example, through software settings, you can define the mutual work coordination mode between each DSP, such as parallel and serial conversion; The workload of each DSP can be easily allocated, and the exchange between master and slave processors can be realized. The slave processor can be upgraded to the master processor as required to be responsible for the allocation of the whole system. When the system detects a DSP fault, it can isolate the faulty processor through software settings, so as to realize the system operation with fault and improve the reliability of the whole system. These operations will involve the operation of the system shared bus, and the problems encountered will be described below

3. Analysis and solution of bus operation problems

3.1 how to select one bus operation to be satisfied with the description of the problem

in the system shown in Figure 1 above, when multiple DSPs work, it is usually necessary to transfer data between processors, status/control words, exchange data with the host, access data to the shared memory, input data from the input device, send data to the output device, etc, These operations will inevitably use the bus. Especially in the real-time environment, when these operations are required to be completed within a limited period of time. In this case, the bus operation encounters the following problems:

(1) when multiple bus occupying operations occur at the same time, bus conflicts often occur if they are not properly allocated. How to avoid bus conflicts

(2) when an operation occupies the bus for a long time, its bus request is not responded, which often leads to bus deadlock. What measures should be taken to solve the bus deadlock problem

(3) when an emergency occurs, the bus needs to be occupied immediately, but the current operation has not released the bus. How can this emergency operation obtain the control of the bus in the shortest time

the specific performance of the above problems when running on the system board is that the program runs unsteadily and often crashes unexpectedly. To solve the above problems, we must establish a reliable bus arbitration mechanism in the system, schedule various bus operations reasonably, so that they do not conflict, and complete their work quickly and correctly. Next, the bus arbitration mechanism in multiprocessor system is analyzed

3.2 analysis of multi processor bus arbitration mechanism

bus arbitration mechanism usually includes two aspects: bus arbitration strategy and bus arbitration mode. The rationality, flexibility, rapidity, realizability and expansibility of the arbitration mechanism are the criteria for evaluating a bus arbitration mechanism

bus arbitration in multiprocessor systems usually includes centralized arbitration and distributed arbitration. The so-called centralized arbitration means that the functions of the bus arbitration component are completed by an additional component independent of each module. If the bus arbitration function is completed by the changing current controller of the bus and needs to be completed by each module, it is called distributed arbitration

the structure of the centralized arbitration mode is shown in Figure 2.

each module has an independent request line and identification line connected to the common arbitration component. The arbitration unit selects the next bus controller according to the corresponding bus arbitration strategy. The advantages of the new energy upsurge caused by the centralized arbitration may begin to explode this year are that the circuit implementation of this arbitration method is relatively simple, the delay of the arbitration device is small, and it has the characteristics of high speed. However, since only one arbitration component is used in the whole structure, centralized arbitration

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